1. Field of the Invention
The present invention relates to a storage interface apparatus for a solid state drive tester, and more particularly to a storage interface apparatus for a solid state drive tester which allows a plurality of interfaces to share a single protocol in parts where the protocol is commonly used to interface storages.
2. Description of the Related Art
Until now, hard disk drives (HDDs) have been most generally known and used as large capacity digital media storage devices. However, in recent years, as prices of NAND flash semiconductor devices, which have the largest capacity among semiconductor devices having a memory function and data stored therein are not erased even when electric power is not supplied, are being lowered, large capacity digital medial storage apparatus such as solid state drives (SSDs) using a semiconductor having a memory function are newly appearing.
Writing and reading speeds of such an SSD are 3 to 5 times as fast as those of existing hard disks, and its performance of reading/writing an random address required by a database management system is several hundreds of times as excellent as those of existing hard disks. In addition, an SSD is operated in a silent way, so a noise problem of an existing hard disk can be solved. Further, since the SSD is operated with power consumption significantly lower than that of a hard disk, the SSD is known as to most suitable for a digital device, such as a laptop computer, which requires low power consumption.
In addition, the SSD has a higher durability against an external impact than an existing hard disk, and as the SSD can be manufactured to be smaller and more various in shape as compared with a hard disk having a fixed form in terms of an external design, an external shape of an electronic product employing the SSD can be made smaller, showing many excellent advantages in its applications.
Due to its advantages, it is expected that distributions of SSDs can be expanded rapidly to searches, home shopping, storage media of video service servers, storage media for storing various R&D materials, and special equipment, as well as existing desktop computers or laptop computers.
A performance of the above-described SSD is tested through an SSD tester, and an SSD test device for testing the SSD according to the related art is illustrated in FIG. 1.
An SSD test device according to the related art includes a host terminal 110, a network 120, a test control unit 130, a memory 140, and an external vector memory 160. In FIG. 1, reference numeral 200 denotes a storage unit 200 including a plurality of storages 201 to 200+N which are test targets.
The host terminal 110 functions to receive a test condition for testing a storage from a user, and the network 120 is in charge of a data interface between the host terminal 110 and the test control unit 130.
A program for testing an SSD is stored in the memory 140, and the external vector memory 160 functions to store pattern data for generating a desired test pattern.
The test control unit 130 functions to generate a test pattern corresponding to the test condition input by the user, adaptively select an interface according to a type of an interface of the storage to be tested to test the storage using the test pattern, and store failure data generated during the test in an internal memory.
Preferably, a plurality of devices installed in the test control unit 130 to test the SSD are implemented as one chip by using a field programmable gate array (FPGA).
The test control unit 130 includes a communication interface unit 131 connected to the host terminal 110 through the network 120 to receive information of the user and to transmit the test result to the host terminal 110, a storage interface unit 132 for interfacing the storage unit 200, and an embedded processor 133 for generating a test pattern corresponding to the test condition input by the user, controlling selection of an interface by the storage interface unit 132 according to an interface type of a storage to be tested, controlling a test of the storage unit 200 through the storage interface unit 132 based on the test pattern, and receiving the result.
The test control unit 130 includes a vector memory 134 for storing expectation data corresponding to the test pattern generated by the embedded processor 133, a failure processor 135 for comparing the expectation data stored in the vector memory 134 with the test result data acquired from the embedded processor 133 to determine a failure, and processing failure information generated in the case of a failure, and a failure memory 136 for storing the failure information generated in the failure processor 135.
Meanwhile, the storage interface unit 132 includes a plurality of multi-interfaces 151 to 151+N.
Here, internal configurations and operations of the plurality of multi-interfaces 151 to 151+N are the same, and thus only one multi-interface 151 will be described below for convenience' sake.
As illustrated in FIG. 2, the multi-interface 151 includes an advanced host controller interface (AHCI) 151a for interfacing instruction data generated in the embedded processor 133, a direct memory access (DMA) unit 151b for interfacing writing data generated in the embedded processor 133, a serial-ATA (SATA) interface 151c for supporting an SATA interface between the advanced host controller interface 151a and the storage 201 and between the direct memory access unit 151b and the storage 201, a serial attached SCSI (SAS) interface 151d for supporting an SAS interface between the advanced host controller interface 151a and the storage 201 and between the direct memory access unit 151b and the storage 201, a PCI express (PCIe) interface 151e for supporting a PCIe interface between the advanced host controller interface 151a and the storage 201 and between the direct memory access unit 151b and the storage 201, and a multiplexer (MUX) 151f for selecting one of the SATA interface 151c, the SAS interface 151d, and the PCIe interface 151e according to an interface selection signal generated in the embedded processor 133 to connect the storage 201 and the embedded processor 133.
Here, the SATA interface 151c, the SAS interface 151d, and the PCIe interface 151e are implemented therein with protocols for independent interfaces, that is, transport layers, transaction layers, link layers, and physical layers, respectively.
In the above-described solid state drive test device according to the related art, a plurality of test devices for testing storages are implemented as one chip by using an FPGA.
In more detail, after a user for testing an SSD connects a solid state drive tester to a storage to be tested, the user inputs a test condition through the host terminal 110. Here, the test condition may contain an interface selection signal for an interface with a storage to be tested.
The test condition of the user input through the host terminal 110 is transferred to the one-chipped test control unit 130 through the network 120.
The communication interface unit 131 of the test control unit 130 receives the test condition input by the user through the network 120, and transfers the received test condition to the embedded processor 133. If the test condition is input by the user and a test is requested, the embedded processor 133 extracts a test program for the storage test from a memory 140 and starts to test the storage. Here, as an initial operation of the test, test pattern data corresponding to the test condition input by the user are extracted from the external vector memory 160 to generate a test pattern.
The generated test pattern is input to the vector memory 134 as expectation data and is transferred to the multi-interface 151 at the same time, and then an interface selection signal is provided to the multi-interface 151 to select an interface corresponding to the storage 201.
For example, an interface selection signal is applied from the embedded processor 133 to the multiplexer 151f of the multi-interface 151, the multiplexer 151f selects one of the interfaces SATA, SAS, and PCIe according to the applied interface selection signal. That is, an interface corresponding to the interface of the storage 201 is selected.
Thereafter, instruction data output from the embedded processor 133 for the test are input to the SATA interface 151c, the SAS interface 151d, and the PCIe interface 151e through the advanced host controller interface 151a, respectively.
In addition, writing data output from the embedded processor 133 are input to the SATA interface 151c, the SAS interface 151d, and the PCIe interface 151e, respectively, through the DMA unit 151b. 
In a state where the instruction data and the writing data output from the embedded processor 133 are input to the respective interfaces in this way, the multiplexer 151f selects only one interface according to an interface selection signal. The test of the storage 201 is started by transferring the instruction data and writing data input to the selected interface to the storage 201. For example, when the interface of the storage 201 uses the SATA interface, the SATA interface 151c is selected, and the instruction data and writing data input to the SATA interface 151c are converted into a format suitable for the SATA interface to be applied to the storage 201.
Here, standard interfaces are employed for the SATA interface, the SAS interface, and the PCIe interface, and protocols for interfaces, that is, protocols for transport layers, link layers, and physical layers are individually implemented in the interfaces, respectively.
Next, after result data for testing the storage 201 are read out according to a reading instruction, they are transferred to the embedded processor 133 through the multiplexer 151f, the SATA interface 151c, and the DMA unit 151b of the multi-interface 151.
If the data obtained by reading out the storage test are transferred to the embedded processor 133, the embedded processor 133 transmits the readout data to the failure processor 135.
The failure processor 135 compares expectation data read out from the vector memory 134 with the readout data (reading data) transferred from the embedded processor 133, and does not generate a failure signal if they are the same and generates a failure signal if they are different.
According to the failure signal generated in this way, the failure memory 136 stores the expectation data and the readout data input to the failure processor 135 as failure information while taking the transferred address as a logical block address (LBA).
In addition, the failure information stored in the failure memory 136 is transferred to the embedded processor 133 according to a request of the embedded processor 133, and is transmitted to the host terminal 110 through the communication interface unit 131 and the network 120.
Thus, the user can recognize the test result of the storage easily tested through the host terminal 110.
However, according to the related art, since interface units are independently manufactured for respective interfaces such as SATA, SAS, and PCIe to be output through the multiplexer, the number of gate counts increases, much heat and noise are generated due to the large sizes of the interfaces, and high implementation costs are required, causing problems in creating a plurality of channels.
For example, according to the related art, protocols are independently provided for respective interfaces, that is, protocols such as transport layers, link layers, and physical layers are provided for respective interfaces, making the size of the interface unit large.